module RAM_SRAM(		//256K x 16
	//	Host Data
	oDATA,
	iDATA,
	iADDR,
	iWE_N,
	iOE_N,
	iCE_N,
	//	SRAM
	SRAM_DQ,
	SRAM_ADDR,
	SRAM_UB_N,
	SRAM_LB_N,
	SRAM_WE_N,
	SRAM_CE_N,
	SRAM_OE_N
);

//	Host Side
input [7:0] iDATA;
output [7:0] oDATA;
input	[18:0] iADDR;
input	iWE_N,iOE_N;
input	iCE_N;
//	SRAM Side
inout [15:0] SRAM_DQ;
output [17:0] SRAM_ADDR;
output SRAM_UB_N, SRAM_LB_N, SRAM_WE_N, SRAM_CE_N, SRAM_OE_N;

assign	SRAM_DQ 	=	SRAM_WE_N ? 16'hzzzz : (SRAM_ADDR[0] ? {iDATA, 8'd0} : {8'd0, iDATA});
assign	oDATA		=	SRAM_ADDR[0] ? SRAM_DQ[15:8] : SRAM_DQ[7:0];
assign	SRAM_ADDR	=	iADDR[18:1];
assign	SRAM_WE_N	=	iWE_N;
assign	SRAM_OE_N	=	iOE_N;
assign	SRAM_CE_N	=	iCE_N;
assign	SRAM_UB_N	=	SRAM_ADDR[0] ? 1'b0 : 1'b1;
assign	SRAM_LB_N	=	SRAM_ADDR[0] ? 1'b1 : 1'b0;

endmodule
